Each block will be discussed step by step:

  ALU — Arithmetic Logical Unit
This unit is used for the arithmetic calculations.

  A-Accumulator
This register is used for arithmetic operations. This is also bit addressable and 8 bit register.

  B-Register
This register is used in only two instructions MUL AB and DIV AB. This is also bit addressable and 8 bit register.

 PC-Program Counter
• Points to the address of next instruction to be executed from ROM
• It is 16 bit register means the 8051 can access program address from 0000H to FFFFH. A total of 64KB of code. 16 bit register means. Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000H)
Final value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (F F F F H)
• Initially PC has 0000H
• ORG instruction is used to initialize the PC ORG 0000H means PC initialize by 0000H
• PC is incremented after each instruction.


Example:

Mnemonics Machine codes
MOV R5, #25H 7D 25
MOV A, #00H 74 00
ADD A, R5 2D
HERE: SJMP HERE; 80 FE
• When 7D is accessed then PC locate the 0001H (next instruction to be executed)
• When 00 is accessed then PC locate the 0004H (next instruction to be executed)

 ROM Memory Map in 8051
→ 4KB, 8KB, 16KB, 32KB, 64KB on chip ROM is available.
→ Max ROM space is 64 KB because 16 bit address line is available in 8051.
→ Starting address for ROM is 0000H (because PC which points the ROM is 16 bit wide).



 8051 Flag Bits and PSW Register

→ Used to indicate the Arithmetic condition of ACC.
→ Flag register in 8051 is called as program status word (PSW). This special function register PSW is also bit addressable and 8 bit wide means each bit can be set or reset independently.



There are four flags in 8051
• P → Parity flag → PSW 0.0
1 – odd number of 1 in ACC
0 – even number of 1 in ACC
• OV(PSW 0.2) → overflow flag → this is used to detect error in signed
arithmetic operation. This is similar to carry flag but difference is only that
carry flag is used for unsigned operation.
• RS1(PSW0.4) RS0(PSW0.3) Register Bank Select

0                              0                            Bank 0
0                              1                            Bank 1
1                              0                            Bank 2
1                              1                            Bank 3

for selecting Bank 1, we use following commands

SETB PSW0.3 (means RS0=1)
CLR PSW0.4 (means RS1=0)

Initially by default always Bank 0 is selected.
• F0 → user definable bit
• AC → Auxiliary carry flag → when carry is generated from D3 to D4, it
is set to 1, it is used in BCD arithmetic.



Since carry is generated from D3 to D4, so AC is set.
•CY → carry flag → Affected after 8 bit addition and subtraction. It is used to detect error in unsigned arithmetic opr. We can also use it as single bit  storage.

SETB C → for cy = 1
CLR C → for cy = 0

 Structure of RAM or 8051 Register Bank and Stack



→ 128 byte RAM is available in 8051
→ 128 byte = 2^7B

Address range of RAM is 00H to 7FH.
→ In MC8051, 128 byte visible or user accessible RAM is available which is shown in figure. Extra 128B RAM which is not user accessible. 80H to FFH used for storage of SFR (special function register)



→ Four Register Banks
→ There are four register banks, in each register bank there are eight 8 bit register available from R0 to R7
→ By default Bank 0 is selected. For Bank 0, R0 has address 00H

R1 has address 01H
. . . . . . . . . . . . . . . .
 . . . . . . . . . . . . . . . .
R7 has address 07H
For Bank 1, R0 has address 08H
R1 has address 09H
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
R7 has address 0FH
For selecting banks we use RS0 and RS1 bit of PSW.
→ R0 to R7 registers are byte addressable means.



 If we want to set the bit 3 of R0 then we can’t use SETB R0.3  We use MOV R0, #08H;
 For changing single bit we can modify all the other bits of R0.
→ Locations 20H to 2FH is bit addressable RAM means each bit from 00H to FFH in this we can set or reset CF rather than changing whole byte.
→ Locations 30H to 7FH is used as scratch pad means we can use this space for data reading and writing or for data storage.


 Stack in 8051
→ RAM locations from 08H to 1FH can be used as stack. Stack is used to store the data temporarily. Stack is last in first out (LIFO)
→ Stack pointer (SP) →
• 8bit register
• It indicate current RAM address available for stack or it points the top of stack.
• Initially by default at 07H because first location of stack is 08H.
• After each PUSH instruction the SP is incremented by one while in MC after PUSH instruction SP is decremented.
• After each POP instruction the SP is decremented.
Example:
MOV R6,#25H;
MOV R1,#12H;
MOV R4,#OF3H;
PUSH 06H;
PUSH 01H;
POP 04H;

→ if we want to use more than 24byte (08H to 1FH) of stack. We can change SP to point RAM address 30H to 7FH by MOV SP, #XX Any value from 30 to 7FH

Conflicting of Register Banks and Stack

→ We know locations from 08H to 1FH is used as stack and it is also used as register bank.
→ If in the program, we use the Register Bank 1 to 3 and also use the stack then conflicts exist and error can be possible. For removing this situation we use the stack from location 30H to 7FH by shifting SP to 2FH. MOV SP,#2FH;

DPTR

→ Data Pointer in 8051
→ 16 bit register, it is divided into two parts DPH and DPL.
→ DPH for Higher order 8 bits, DPL for lower order 8 bits.
→ DPTR, DPH, DPL these all are SFRs in 8051.

Special Function Register

→ (See Fig.) RAM scratch pad, there is extra 128 byte RAM which is used to store the SFRs

→ Following figure shows special function bit address, all access to the four I/O ports CPU register, interrupt control register, timer/counter, UART, power control are performed through registers between 80H and FFH.





Byte Addressable SFR with byte address
SP – Stack printer – 81H
DPTR – Data pointer 2 bytes
DPL – Low byte – 82H
DPH – High byte – 83H
TMOD – Timer mode control – 89H
TH0 – Timer 0 Higher order bytes – 8CH
TL0 – Timer 0 Low order bytes – 8AH
TH1 – Timer 1 High bytes = 80H
TL1 – Timer 1 Low order byte = 86H
SBUF – Serial data buffer = 99H
PCON – Power control – 87H.